Quantum dot cellular automata (QCA) constitute an emergent nanoscale-based digital nanoelectronics technology with comprehensive applications in nanocomputing based on the small nanometer size of such circuits and their ultralow power consumption, fast operation, and high clock frequency in comparison with transistor-based complementary metal–oxide–semiconductor (CMOS) technologies. A novel design for edge-triggered synchronous J-K flip-flop (FF) and D (data or delay) flip-flop memory elements based on QCA cells with quantum wires is presented herein. The proposed design has fewer QCA cells and lower latency and area and uses the coplanar crossover method to overcome the complexity of multilayer quantum wire crossing. The design is analyzed to determine the average output polarization (AOP) of the edge-triggered synchronous D-FF and JK-FF at different temperature levels and the optimized energy dissipation. The layout design and computational simulation of the circuit are carried out using QCADesigner V. 2.0.3 software, while the energy dissipation is analyzed using the QCADesigner-E V. 2.2 tool.

中文翻译：

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利用量子点元胞自动机的边沿触发同步存储元件的高效设计和优化的能量耗散

量子点元胞自动机（QCA）构成了一种新兴的基于纳米级的数字纳米电子技术，基于此类电路的小纳米尺寸以及与基于晶体管的互补电路相比，它们的超低功耗，快速运行和高时钟频率，在纳米计算中得到了广泛的应用。金属氧化物半导体（CMOS）技术。本文提出了一种基于具有量子线的QCA单元的边缘触发同步JK触发器（FF）和D（数据或延迟）触发器存储元件的新颖设计。所提出的设计具有更少的QCA单元，更低的等待时间和面积，并使用共面交叉方法来克服多层量子线交叉的复杂性。分析设计以确定在不同温度水平下边沿触发的同步D-FF和JK-FF的平均输出极化（AOP），以及优化的能量耗散。使用QCADesigner V. 2.0.3软件进行电路的布局设计和计算仿真，同时使用QCADesigner-E V. 2.2工具分析能耗。