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A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection
Integration ( IF 2.2 ) Pub Date : 2020-05-14 , DOI: 10.1016/j.vlsi.2020.04.001
Rajit Karmakar , Suman Sekhar Jana , Santanu Chattopadhyay

A popular countermeasure against IP piracy is to obfuscate the Finite State Machine (FSM) which is assumed to be the heart of a digital system. Most of the existing FSM obfuscation strategies rely on additionally introduced set of obfuscation mode state-transitions to protect the original state-transitions of the FSM. Although these methods assume that it is difficult to extract the FSM behavior from the flattened gate-level netlist, some recent reverse engineering attacks could successfully break the defense of these schemes. The capability of differentiating obfuscation mode state-transitions from normal mode state-transitions makes these attacks powerful. As a countermeasure against these attacks, we propose a new strategy that offers a key-based obfuscation to each state-transition of the FSM. We use a special class of non-group additive cellular automata (CA), called D1 ∗ CA, and it's counterpart D1∗CAdual to obfuscate each state-transition of the FSM. Each state-transition has its own customized key, which must be configured correctly in order to get correct state-transition behavior from the synthesized FSM. A second layer of protection to the state-transition logic enhances the security of the proposed scheme. An in-depth security analysis of the proposed easily testable key-controlled FSM synthesis scheme demonstrates its ability to thwart the majority of the state-of-the-art attacks, such as FSM reverse engineering, SAT, and circuit unrolling attacks. Thus, the proposed scheme can be used for IP protection of the digital designs. Experimentations on various IWLS′93 benchmark FSM designs show that the average area, power, and delay overheads our proposed multi-bit key-based obfuscated FSM design are 56.43%, 6.87%, and 23.41% while considering the FSMs as standalone circuits. However, experimentation on the Amber23 processor core shows these overheads drastically reduce (reported area, power, and delay overheads values are 0.0025%, 0.44%, and 0%, respectively) while compared with respect to the entire design.



中文翻译:

元胞自动机指导有限状态机的两级混淆处理,以保护IP

防止IP盗版的一种流行对策是模糊化有限状态机(FSM),后者被认为是数字系统的核心。现有的大多数FSM模糊处理策略都依赖于额外引入的模糊处理模式状态转换集来保护FSM的原始状态转换。尽管这些方法假定很难从扁平化的门级网表中提取FSM行为,但是最近的一些逆向工程攻击可能会成功打破这些方案的防御能力。区分混淆模式状态转换与正常模式状态转换的能力使这些攻击变得强大。作为对付这些攻击的对策,我们提出了一种新策略,该策略为FSM的每个状态转换提供了基于密钥的混淆。D 1 ∗  CA,与之相对应的D 1 ∗ CA对混淆FSM的每个状态转换。每个状态转换都有其自己的自定义密钥,必须对其进行正确配置,以便从合成的FSM获得正确的状态转换行为。状态转换逻辑的第二层保护增强了所提出方案的安全性。对该提议的易于测试的密钥控制的FSM综合方案进行的深入安全性分析表明,它可以阻止大多数最新的攻击,例如FSM逆向工程,SAT和电路展开攻击。因此,所提出的方案可以用于数字设计的IP保护。对各种IWLS'93基准FSM设计进行的实验表明,我们提出的基于多位密钥的模糊FSM设计的平均面积,功率和延迟开销为56.43%,6.87%和23。将FSM视为独立电路时占41%。但是,在Amber23处理器内核上进行的实验表明,与整个设计相比,这些开销大大减少了(报告的面积,功率和延迟开销分别为0.0025%,0.44%和0%)。

更新日期:2020-05-14
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