This research article presents an implementation of high-performance Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) core for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM)-based applications. The radix-2 butterflies are implemented using arithmetic optimization technique which reduces the number of complex multipliers involved. High-performance approximate multipliers with negligible error rate are used to eliminate the power-consuming complex multipliers in the radix-2 butterflies. The FFT/IFFT prototype using the proposed high-performance butterflies are implemented using Altera Quartus EP2C35F672C6 Field Programmable Gate Array (FPGA) which yields 40% of improved logic utilization, 33% of improved timing parameters, and 14% of improved throughput rate. The proposed optimized radix-2-based FFT/IFFT core was also implemented in 45-nm CMOS technology library, using Cadence tools, which occupies an area of 143.135 mm² and consumes a power of 9.10 mW with a maximum throughput of 48.44 Gbps. Similarly, the high-performance approximate complex multiplier-based optimized FFT/IFFT core occupies an area of 64.811 mm² and consumes a power of 6.18 mW with a maximum throughput of 76.44 Gbps.

中文翻译：

---

面向MIMO-OFDM应用的区域高效节能FFT / IFFT核心的VLSI实现

本文针对基于多输入多输出正交频分复用（MIMO-OFDM）的应用，提出了高性能快速傅里叶变换（FFT）和逆快速傅里叶变换（IFFT）内核的实现。基2蝶形是使用算术优化技术实现的，该算法可减少涉及的复数乘法器的数量。误差率可忽略的高性能近似乘法器用于消除基数2蝶形中耗能的复数乘法器。使用Altera Quartus EP2C35F672C6现场可编程门阵列（FPGA）实现了使用拟议的高性能蝶形的FFT / IFFT原型，FPGA的逻辑利用率提高了40％，时序参数提高了33％，吞吐率提高了14％。²，功耗为9.10 mW，最大吞吐量为48.44 Gbps。同样，基于高性能近似复杂乘法器的优化FFT / IFFT内核占地64.811 mm ²，功耗为6.18 mW，最大吞吐量为76.44 Gbps。