The most challenging aspect of particle filtering hardware implementation is the resampling step. This is because of high latency as it can be only partially executed in parallel with the other steps of particle filtering and has no inherent parallelism inside it. To reduce the latency, an improved resampling architecture is proposed which involves pre-fetching from the weight memory in parallel to the fetching of a value from a random function generator along with architectures for realizing the pre-fetch technique. This enables a particle filter using M particles with otherwise streaming operation to get new inputs more often than 2M cycles as the previously best approach gives. Results show that a pre-fetch buffer of five values achieves the best area-latency reduction trade-off while on average achieving an 85% reduction in latency for the resampling step leading to a sample time reduction of more than 40%. We also propose a generic division-free architecture for the resampling steps. It also removes the need of explicitly ordering the random values for efficient multinomial resampling implementation. In addition, on-the-fly computation of the cumulative sum of weights is proposed which helps reduce the word length of the particle weight memory. FPGA implementation results show that the memory size is reduced by up to 50%.

粒子滤波硬件实现中最具挑战性的方面是重采样步骤。这是由于高延迟，因为它只能与粒子过滤的其他步骤并行地部分执行，并且内部没有固有的并行性。为了减少等待时间，提出了一种改进的重采样体系结构，该体系结构涉及从权重存储器中进行预取与从随机函数发生器中获取值并行进行，同时还涉及用于实现预取技术的体系结构。这使得使用M个粒子并进行流操作的粒子滤波器能够获得比2 M更多的新输入按照以前最好的方法进行循环。结果表明，五个值的预取缓冲器实现了最佳的区域延迟减少权衡，而平均而言，重采样步骤的延迟减少了85 ％，从而使采样时间减少了40％以上。我们还为重采样步骤提出了一种通用的无除法架构。它还消除了为高​​效的多项式重采样实现显式排序随机值的需要。另外，提出了对累积的权重之和进行动态计算，这有助于减少粒子权重存储器的字长。FPGA实施结果表明，存储器大小最多减少了50％。