ABSTRACT A low spur frequency synthesiser is proposed based on the frequency-hopping spread spectrum which is employed on the control voltage of the voltage-controlled oscillator. A spur reduction circuit is inserted between the phase-frequency detector and charge pump to randomly shift the spur to higher frequencies to suppress the reference spur. In order to achieve this, the proposed technique uses the time to voltage converter and the voltage to time converter and a linear feedback shift register. Through shifting and randomising the periodic ripples on the control voltage to high frequencies, the amplitude of the reference spur is attenuated. The proposed structure eliminates the need for decreasing bandwidth and reducing the VCO gain to suppress the reference spur. A 2.08–2.22 GHz frequency synthesiser is designed and a post-layout simulation is performed using the 180 nm CMOS technology. The reference spur level of −91.25 dBc is achieved. The presented structure provides an additional spur reduction of 32.88 dB compared to a conventional frequency synthesiser and also provides the best-normalised reference spur rejection in the literature. Settling time is obtained when the output frequency is switched from 2.1 to 2.08 GHz.

中文翻译：

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低杂散频率合成器使用随机移位的参考杂散到更高的频率

摘要 基于对压控振荡器的控制电压采用跳频扩频，提出了一种低杂散频率合成器。在相位频率检测器和电荷泵之间插入一个杂散抑制电路，将杂散随机移至更高的频率，以抑制参考杂散。为了实现这一点，所提出的技术使用时间电压转换器和电压时间转换器以及线性反馈移位寄存器。通过将控制电压上的周期性纹波移动和随机化为高频，参考杂散的幅度被衰减。建议的结构消除了降低带宽和降低 VCO 增益以抑制参考杂散的需要。A 2.08–2。设计了 22 GHz 频率合成器，并使用 180 nm CMOS 技术进行了布局后仿真。达到了 −91.25 dBc 的参考杂散电平。与传统频率合成器相比，所提出的结构提供了 32.88 dB 的额外杂散降低，并且还提供了文献中最佳归一化参考杂散抑制。当输出频率从 2.1 GHz 切换到 2.08 GHz 时获得稳定时间。