ABSTRACT Quantum-dot cellular automata (QCA), which has very high speed and very low area and power consumption, is one of the proposed nanotechnologies to design digital electronic circuits. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are two important blocks in transceiver circuit design. The phase-frequency detector (PFD), which measures the phase and frequency differences of two signals, is one of the main blocks in PLLs and DLLs architectures. In this paper, two novel phase-frequency detector designs have been proposed in QCA technology using rising and falling edge D flip-flops with reset ability. The proposed PFDs can provide the basis for designing larger circuits such as phase-locked loops and delay-locked loops that are widely used in communication systems. The two proposed structures for the phase-sensitive detector in quantum cellular automata technology, which detect the phase differences of rising and falling edges of their inputs, are composed of 174 and 170 cells, occupying only 0.27 and 0.26 μm2, respectively. Smaller area, better jitter performance, smaller glitch and reset path time, higher operating frequency and lower power consumption are the main advantages of proposed designs in comparison with CMOS PFDs. All the simulations are done by QCADesigner software and QCAPro Software.

中文翻译：

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使用带复位端的D触发器设计QCA纳米技术中的PFD

摘要 量子点元胞自动机（QCA）具有非常高的速度和非常低的面积和功耗，是设计数字电子电路的纳米技术之一。锁相环 (PLL) 和延迟锁定环 (DLL) 是收发器电路设计中的两个重要模块。相位频率检测器 (PFD) 可测量两个信号的相位和频率差，是 PLL 和 DLL 架构中的主要模块之一。在本文中，使用具有复位能力的上升沿和下降沿 D 触发器，在 QCA 技术中提出了两种新颖的相位频率检测器设计。所提出的 PFD 可以为设计更大的电路提供基础，例如在通信系统中广泛使用的锁相环和延迟锁定环。量子细胞自动机技术中的相敏检测器的两种提议结构，用于检测其输入上升沿和下降沿的相位差，由174和170个单元组成，分别仅占0.27和0.26 μm2。与 CMOS PFD 相比，更小的面积、更好的抖动性能、更小的毛刺和复位路径时间、更高的工作频率和更低的功耗是所提议设计的主要优势。所有的模拟都是由 QCADesigner 软件和 QCAPro 软件完成的。与 CMOS PFD 相比，更高的工作频率和更低的功耗是所提议设计的主要优势。所有的模拟都是由 QCADesigner 软件和 QCAPro 软件完成的。与 CMOS PFD 相比，更高的工作频率和更低的功耗是所提议设计的主要优势。所有的模拟都是由 QCADesigner 软件和 QCAPro 软件完成的。