ABSTRACT Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currents and one-tenth the off-currents than the equally sized MOSFETs at the same technology node, making them ideal candidates for ultra-low-power VLSI applications. This paper presents a complementary GOTFET (CGOT) based dynamic full adder (DFA), which consumes significantly lower power than conventional CMOS DFAs and operates at double the speed of CMOS DFAs. A conventional DFA designed using GOTFETs instead of MOSFETs exhibits 100 ps (40%) lower & 50 ps (30%) lower delays than CMOS DFA. Furthermore, the CGOT DFA consumes merely 2.6 pW of static power, which is 99% (2 orders) lower than the corresponding CMOS DFA ., , . This paper proposes a novel improved DFA circuit design, which mitigates the dynamic power by eliminating redundant switching activity within the DFA circuit, . The proposed modified DFA topology reduces the total power consumption by 25% than the conventional DFA designs at 50% switching activity. The overall power delay product (PDP) reduces to merely 0.9% of the standard CMOS designs. The total power consumption reduces even further with decreasing switching activity, and the improved CGOT DFA consumes 31% lower total power (at 25% switching activity).

中文翻译：

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一种新型超低功耗栅极重叠隧道 FET (GOTFET) 动态加法器

摘要 最近的研究表明，在相同技术节点，栅极重叠隧道 FET (GOTFET) 的导通电流是相同尺寸的 MOSFET 的两倍，截止电流是其十分之一，使其成为超低功耗的理想选择。超大规模集成电路应用。本文介绍了一种基于互补 GOTFET (CGOT) 的动态全加器 (DFA)，它的功耗比传统 CMOS DFA 低得多，并且运行速度是 CMOS DFA 的两倍。使用 GOTFET 而不是 MOSFET 设计的传统 DFA 表现出比 CMOS DFA 低 100 ps (40%) 和 50 ps (30%) 的延迟。此外，CGOT DFA 的静态功耗仅为 2.6 pW，比相应的 CMOS DFA 低 99%（2 个数量级）。本文提出了一种新颖的改进型 DFA 电路设计，它通过消除 DFA 电路中的冗余开关活动来减轻动态功率，。与传统的 DFA 设计相比，在 50% 的开关活动下，所提议的修改后的 DFA 拓扑将总功耗降低了 25%。整体功率延迟积 (PDP) 减少到标准 CMOS 设计的仅 0.9%。随着开关活动的减少，总功耗进一步降低，改进后的 CGOT DFA 的总功耗降低了 31%（开关活动为 25%）。