ABSTRACT This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximises the sharing of common hardware circuit and achieves the area-delay efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 16384 × 16384 points target synthetic aperture radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T field programmable gate array platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.

中文翻译：

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用于浮点运算的统一可重构 CORDIC 处理器

摘要 本文提出了一种用于浮点运算的统一可重构坐标旋转数字计算机 (CORDIC) 处理器。可配置多模运行，实现多种操作，替代多个单模CORDIC处理器。提出了一种可重构流水线并行混合架构来适应不同的操作，最大限度地共享公共硬件电路并实现区域延迟效率。与之前统一的浮点CORDIC处理器相比，硬件资源的消耗大大降低。作为概念验证，我们将其应用于在 Xilinx XC7VX690T 现场可编程门阵列平台上实现的 16384 × 16384 点目标合成孔径雷达 (SAR) 成像系统。