ABSTRACT Domino circuit topology for high-speed operation, robustness and lower power consumption is quintessential in design of digital systems. In this paper, various high speed and robust mechanisms are proposed to enhance the speed of Clock-Delayed Dual Keeper Domino (CDDK) circuit. Delayed enabling of keeper circuit in CDDK domino circuit reduces contention between keeper circuit and Pull-Down network (PDN). The speed of transition at the dynamic node of the CDDK domino circuit is enhanced through imposing techniques namely (i) controlled clock delay time in enabling the keeper transistor, (ii) keeper control signal voltage swing variation, (iii) sizing of keeper transistors and (iv) deploying an additional conditional discharge path. The robustness of CDDK circuit is increased by upsizing the keeper transistor without degrading the speed by stack arrangement of dual keeper transistors. The simulation of enhancement techniques has been performed using Cadence® Virtuoso ADEL and ADEXL environments employing UMC 90nm technology library. The simulation results of wide fan-in 64-input OR gate demonstrate that CDDK technique with additional discharge path offer 38% increase in speed and CDDK technique with keeper transistor upsizing offers 52% increase in noise gain margin without speed degradation while comparing with the conventional domino logic circuit.

中文翻译：

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时钟延迟双保持器多米诺逻辑风格的速度增强技术

摘要 用于高速操作、鲁棒性和低功耗的 Domino 电路拓扑结构是数字系统设计的精髓。在本文中，提出了各种高速和稳健的机制来提高时钟延迟双保持器多米诺 (CDDK) 电路的速度。CDDK 多米诺电路中保持电路的延迟启用减少了保持电路和下拉网络 (PDN) 之间的争用。CDDK 多米诺电路的动态节点处的转换速度通过强加技术得到增强，即 (i) 启用保持器晶体管时的受控时钟延迟时间，(ii) 保持器控制信号电压摆动变化，(iii) 保持器晶体管的尺寸和(iv) 部署额外的有条件放电路径。CDDK 电路的鲁棒性通过增大保持器晶体管的尺寸而增加，而不会通过双保持器晶体管的堆叠布置降低速度。增强技术的仿真是使用采用 UMC 90nm 技术库的 Cadence® Virtuoso ADEL 和 ADEXL 环境进行的。宽扇入 64 输入 OR 门的仿真结果表明，与传统相比，具有额外放电路径的 CDDK 技术可将速度提高 38%，而保持晶体管尺寸增大的 CDDK 技术可在不降低速度的情况下将噪声增益裕度提高 52%多米诺逻辑电路。