Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of $O$(100 $\mu$s) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of $\pm$ 30%. Inferring a critical current $I_{\rm c}$ variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in $<$ 3.5% relative standard deviation (RSD) in critical current ($\equiv \sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm$^2$. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown $\sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having $\sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ $<$ 1.0% (equivalent to $\sigma_{f}/\left\langle f \right\rangle$ $<$ 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.

中文翻译：

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改善超导量子相干电路中的晶圆级约瑟夫森结电阻变化

量子位或量子位是为下一代计算机和探测器设想的相干电路的一个例子。一个具有 $O$(100 $\mu$s) 相干寿命的稳健超导量子位是 transmon：约瑟夫森结作为非线性电感器与电容器并联以形成非谐波振荡器。在具有许多此类传输器的复杂设备中，通常需要对每个量子位频率进行精确控制，因此必须充分减少结面积和隧道势垒厚度的变化，以实现最佳性能，同时避免相邻电路之间的光谱重叠。简单地将我们针对单个独立设备优化的配方移植到晶圆级（从 150 毫米晶圆生产 64、1x1 厘米的芯片）最初导致室温隧道电阻的全局漂移 30%。从该电阻分布推断临界电流 $I_{\rm c}$ 的变化，我们提出了一种优化的工艺，该工艺由系统的 38 片晶圆研究开发，导致临界电流 ($\等效 \sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$) 用于 49 cm$^2 区域的 3000 个约瑟夫森结（单结和非对称 SQUID） $. 在基板上的 1x1 厘米移动窗口内观察可以估计给定量子位芯片的变化特征。我们利用超声波辅助显影、均匀灰化和动态氧化的最佳工艺显示 $\sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ = 1.8% in 1x1 cm ，平均而言，一些 1x1 厘米的区域具有 $\sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ $<$ 1。0%（相当于 $\sigma_{f}/\left\langle f \right\rangle$ $<$ 0.5%）。这种稳定性将大大提高具有严格临界电流要求的多结芯片的良率。