Many integrated electrical circuits and networks comprise of large RLC ladders. These complex circuits are described by high-order positive-real transfer functions. To simplify the design and analysis of these complex systems, model reduction techniques are used. It is of critical importance that the positive-real structure of the transfer function is retained in the reduction process. Moreover, it is often of the interest that the reduced-order surrogate model accurately approximates the original system within a limited time or frequency range. In this paper, truncated balanced realizations which ensure good accuracy in the desired time or frequency range without losing the positive-real structure of the original system are presented. These realizations can even be computed for non-minimal systems. Easily computable a priori error bound expressions are also derived for the proposed algorithms. The algorithms are tested on benchmark examples and comparison with the existing techniques is shown to highlight the efficacy of the proposed algorithms.

中文翻译：

---

时间/频率限制的正实截断平衡实现

许多集成电路和网络都由大型RLC阶梯组成。这些复杂的电路由高阶正实传递函数描述。为了简化这些复杂系统的设计和分析，使用了模型简化技术。至关重要的是，在简化过程中保留传递函数的正实结构。而且，通常感兴趣的是降阶代理模型可以在有限的时间或频率范围内准确地逼近原始系统。在本文中，提出了截断的平衡实现，这些实现可确保在所需时间或频率范围内保持良好的精度，而又不会丢失原始系统的正实结构。这些实现甚至可以针对非最小系统进行计算。易于计算还针对所提出的算法推导了先验误差界表达式。该算法在基准示例上进行了测试，并与现有技术进行了比较，以突出所提出算法的有效性。