In this paper, we exploit the aggressive supply voltage underscaling technique in Block RAMs (BRAMs) of Field Programmable Gate Arrays (FPGAs) to improve the energy efficiency of Multi-Layer Perceptrons (MLPs). Additionally, we evaluate and improve the resilience of this accelerator. Through experiments on several representative FPGA fabrics, we observe that until a minimum safe voltage level, i.e., Vmin the MLP accuracy is not affected. This safe region involves a large voltage guardband. Also, it involves a narrower voltage region where faults start to appear in memories due to the increased circuit delay, but these faults are masked by MLP, and thus, its accuracy is not affected. However, further undervolting causes significant accuracy loss as a result of the fast-increasing high fault rates. Based on the characterization of these undervolting faults, we propose fault mitigation techniques that can effectively improve the resilience behavior of such accelerator. Our evaluation is based on four FPGA platforms. On average, we achieve >90% energy saving with a negligible accuracy loss of up to 0.1%.

中文翻译：

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低电压 FPGA BRAM 操作下多层感知器 (MLP) 的功率和精度

在本文中，我们利用现场可编程门阵列 (FPGA) 的块 RAM (BRAM) 中的激进电源电压缩放技术来提高多层感知器 (MLP) 的能效。此外，我们评估并提高了该加速器的弹性。通过对几个有代表性的 FPGA 结构的实验，我们观察到，直到达到最小安全电压电平，即 Vmin，MLP 精度才不会受到影响。这个安全区域涉及一个大的电压保护带。此外，它涉及更窄的电压区域，由于电路延迟增加，存储器中开始出现故障，但这些故障被 MLP 屏蔽，因此其准确性不受影响。然而，由于快速增加的高故障率，进一步的欠压会导致显着的精度损失。基于这些欠电压故障的特征，我们提出了故障缓解技术，可以有效改善此类加速器的弹性行为。我们的评估基于四个 FPGA 平台。平均而言，我们实现了 90% 以上的节能，而准确度损失可忽略不计，最高可达 0.1%。