Design of adder plays a major role in deciding overall performance of system as it is a major building block through generations of design in an innovative design of circuits. In VLSI system and signal processing field applications, various versions of adders are utilized. In applications of signal processing, in recent days, major role is contributed by Finite Impulse Response (FIR) filter. Various authors and papers described its design in a several ways. With the design of effective multiplier, signal denoising application was not explained by any of the existing works. For the generation of partial products, 8-bit multiplier based on a Vedic Mathematics –UrdhvaTiryagbhyam sutra- is proposed in this work. In Vedic multiplier, carry skip method is used for realizing addition of partial product. Four Vedic multipliers of 4 × 4 size are used for designing 8-bit multiplier. Carry skip and UrdhvaTiryagbhyam methods are used for this design. For addition of partial product, this multiplier is designed. Ripple carry adder's logic levels are modified for adding these Vedic multiplier's output. Powerful elimination of ECG noise can be done using this proposed fast FIR filter. In applications of healthcare and biomedical field, they are used. In Vedic design, Ripple Carry Adder (RCA) is used for carrying out partial product addition. Operation of FIR filter with Electro Cardiogram (ECG) signal is done by proposing architecture of FIR filter. It is termed as PPAVD-RCA-FIR and used in de-noising applications. From de-noised signal, Signal to Noise Ratio (SNR), Bit Error Rate (BER) and Mean Square Error (MSE) are computed, which are used for evaluating the performances. When compared with general Vedic multiplier, speed of the proposed design is increased about 13.65% as shown by results.

加法器的设计在决定系统的整体性能方面起着重要作用，因为它是电路创新设计中经过几代设计的重要组成部分。在VLSI系统和信号处理现场应用中，使用了各种版本的加法器。在信号处理的应用中，近来，有限脉冲响应（FIR）滤波器发挥了重要作用。许多作者和论文以几种方式描述了它的设计。通过有效乘法器的设计，现有的任何工作都没有说明信号去噪的应用。为了生成部分乘积，在这项工作中，提出了基于吠陀数学的8位乘法器–乌德瓦（UrdhvaTiryagbhyam sutra）。在吠陀乘法器中，进位跳跃法用于实现部分乘积的相加。四个4×4大小的吠陀乘法器用于设计8位乘法器。此设计使用了进位跳过和UrdhvaTiryagbhyam方法。为了增加部分乘积，设计了该乘数。修改了纹波进位加法器的逻辑电平，以将这些吠陀乘法器的输出相加。使用此建议的快速FIR滤波器可以有效消除ECG噪声。在医疗保健和生物医学领域的应用中，它们被使用。在吠陀设计中，纹波携带加法器（RCA）用于进行部分产品添加。通过提出FIR滤波器的架构来完成带有心电图（ECG）信号的FIR滤波器的操作。它被称为PPAVD-RCA-FIR，用于去噪应用。根据去噪后的信号，计算信噪比（SNR），误码率（BER）和均方误差（MSE），用于评估性能。结果表明，与普通吠陀乘法器相比，拟议设计的速度提高了约13.65％。