Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, V_ddmin, on each die that does not cause SRAM read and write failures, which are majorities of SRAM failures, under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, V_fail, that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM ${\hat{V}}_{ddmin}$ on each die from the measured V_fail of SRAM monitor on the same die where V_fail-V_ddmin correlation table is built-up in design infra development phase, and ${\hat{V}}_{ddmin}$ can be directly derived from the measured V_fail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 10.45%, read energy by 4.99%, and write energy by 5.45% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint. In addition, the effect of IR drop and process variations of peripheral circuit on V_ddmin prediction is taken into account by reflecting them on SRAM bitcell operation. We also solidify our V_ddmin prediction methodology by considering the prevention of potential SRAM access failures for high-speed designs as well as the SRAM read and write failures.

通过近阈值电压（NTV）操作进行低功耗设计非常有吸引力，因为它可以大大减轻功耗的急剧增加。但是，使用NTV操作的一个主要障碍是SRAM故障的显着增加。在这项工作中，我们提出了一种片上SRAM监视方法，该方法能够在目标置信度下准确预测不会导致SRAM读写故障（这是大多数SRAM故障）的每个管芯上的最小电压V _ddmin。水平。确切地说，我们提出了一个SRAM监视器，从中我们可以测量最大电压V _fail，该最大电压_会导致该SRAM监视器发生功能故障。然后，我们提出了一种推断SRAM的新方法${\hat{V}}_{dd米\mathrm{一世}ñ}$由所测量的每个管芯V_失败在同一裸片上，其中SRAM显示器的V_失败- V _ddmin相关表是建成在下文设计开发阶段，和${\hat{V}}_{dd米\mathrm{一世}ñ}$可以直接从测量的V _fail得出，并参考硅生产阶段的相关表。通过实验，我们证实，与通过对所有裸片施加相同的最小电压同时满足相同的最小要求相比，我们提出的方法能够在SRAM位单元阵列中节省10.4％的泄漏功率，4.99％的读取能量以及5.45％的写入能量。产量约束。另外，通过将IR压降和外围电路的工艺变化对V _ddmin预测的影响考虑在内，将其反映在SRAM位单元操作上。我们还固化了V _ddmin 通过考虑防止对高速设计潜在的SRAM访问失败以及SRAM读写失败的预测方法。