This paper presents a new digital background calibration method to correct MDAC errors. The novelty of this research is to use Newton–Raphson algorithm in order to reduce the number of divisions as well as power in digital domain. This is achieved by combining the conventional slope mismatch averaging and linear approximation technique to compute the correction coefficient in fast iterative method. To validate the accuracy of the proposed method, the digital part of the calibration scheme is implemented on FPGA. The superiorities of the proposed method are fast convergence time, less power consumption, and less digital complexity in compared to previous studies. These benefits are due to using split structure along with Newton–Raphson method. Several simulations of a 12-bit 100MS/s pipelined ADC indicate that SNDR/SFDR is improved from 30/33 dB to 70/79 dB after calibration. Calibration process is achieved in approximately 2000 clock cycles. The proposed ADC achieves a FoM of 0.03-pJ/conversion-step and consumes an analog power of 6.7 mW.

本文提出了一种新的数字背景校准方法来纠正MDAC错误。这项研究的新颖之处在于使用Newton-Raphson算法以减少数字域中的划分数量和功率。这是通过结合常规的斜率失配平均和线性近似技术以快速迭代方法计算校正系数来实现的。为了验证所提方法的准确性，在FPGA上实现了校准方案的数字部分。与以前的研究相比，该方法的优点是收敛速度快，功耗低，数字复杂度低。这些好处归因于使用分裂结构以及牛顿-拉夫森方法。12位100MS / s流水线ADC的一些仿真表明，校准后SNDR / SFDR从30/33 dB提高到70/79 dB。校准过程大约需要2000个时钟周期。拟议的ADC的FoM为0.03pJ /转换步长，模拟功耗为6.7mW。