Due to the growing complexity of today’s digital circuits, the speed of fault simulation has become increasingly important. Although critical path tracing (CPT) is faster than conventional methods, it is not fast enough for fault simulation of complex circuits with a large number of faults and tests. Exact stem analysis is the most important obstacle in accelerating the CPT method. The simplification of stem analysis eliminates time-consuming computations and makes the CPT method more parallelizable. An approximate and bit-parallel CPT algorithm is proposed for ultrafast fault simulation for both stuck-at-fault (SAF) and transition delay fault (TDF) models. Time linearity, speedup, and accuracy of the proposed algorithm are examined and evaluated using ISCAS85, ISCAS89, and ITC99 benchmark circuits. In order to assess the accuracy, the false-positive and false-negative detection of faults are counted for each benchmark circuit. The experimental results reveal considerable speedup as well as acceptable accuracy of the proposed approach in comparison with the traditional methods and commercial fault simulators.

中文翻译：

---

使用近似并行关键路径跟踪进行故障模拟的简单快速解决方案

由于当今数字电路日益复杂，故障模拟的速度变得越来越重要。尽管关键路径追踪（CPT）比传统方法更快，但对于具有大量故障和测试的复杂电路的故障模拟来说，速度还不够快。精确词干分析是加速 CPT 方法的最重要障碍。词干分析的简化消除了耗时的计算并使 CPT 方法更具并行性。针对固定故障 (SAF) 和转换延迟故障 (TDF) 模型，提出了一种近似和位并行 CPT 算法，用于超快故障仿真。使用 ISCAS85、ISCAS89 和 ITC99 基准电路检查和评估所提出算法的时间线性度、加速比和准确性。为了评估准确性，为每个基准电路计算错误的假阳性和假阴性检测。实验结果表明，与传统方法和商业故障模拟器相比，所提出的方法具有显着的加速和可接受的精度。