LiteX is a GitHub-hosted SoC builder / IP library and utilities that can be used to create SoCs and full FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely described using Migen Python internal DSL, which simplifies its design in depth. LiteX already supports various softcores CPUs and essential peripherals, with no dependencies on proprietary IP blocks or generators. This paper provides an overview of LiteX: two real SoC designs on FPGA are presented. They both leverage the LiteX approach in terms of design entry, libraries and integration capabilities. The first one is based on RISC-V core, while the second is based on a LM32 core. In the second use case, we further demonstrate the use of a fully open-source toolchain coupled with LiteX.

中文翻译：

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LiteX：基于 Migen Python DSL 的开源 SoC 构建器和库

LiteX 是 GitHub 托管的 SoC 构建器/IP 库和实用程序，可用于创建 SoC 和完整的 FPGA 设计。除了开源和 BSD 许可外，其独创性还在于其 IP 组件完全使用 Migen Python 内部 DSL 进行描述，从而深度简化了其设计。LiteX 已经支持各种软核 CPU 和基本外围设备，不依赖于专有 IP 块或生成器。本文提供了 LiteX 的概述：介绍了两个基于 FPGA 的真实 SoC 设计。它们都在设计输入、库和集成功能方面利用了 LiteX 方法。第一个基于 RISC-V 内核，而第二个基于 LM32 内核。在第二个用例中，我们进一步演示了与 LiteX 结合使用的完全开源工具链的使用。