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Hybrid sorting algorithm implemented by High Level Synthesis
IEEE Latin America Transactions ( IF 1.3 ) Pub Date : 2020-05-04 , DOI: 10.1109/tla.2020.9085300
Luciana De Micco 1 , Mariano L. Acosta 1 , Maximiliano Antonelli 1
Affiliation  

This paper proposes a hybrid data ordering algorithm which executes serial and parallel instructions. The implementation of the system is presented in the Zedboard development board of Xilinx that includes a SoC (System on Chip). The design was done in high level language HLS (High Level Synthesis). It receives a vector of N elements and delivers the set of indexes of the L major elements ordered. The complexity of the algorithm is analyzed in a generic way. The required times and resources are evaluated and compared with well known sorting algorithms.

中文翻译:


High Level Synthesis 实现的混合排序算法



本文提出了一种执行串行和并行指令的混合数据排序算法。该系统的实现在 Xilinx 的 Zedboard 开发板上进行,其中包括 SoC(片上系统)。该设计是用高级语言HLS(高级综合)完成的。它接收一个由 N 个元素组成的向量,并传递 L 个主要元素的有序索引集。以通用的方式分析算法的复杂度。评估所需的时间和资源,并与众所周知的排序算法进行比较。
更新日期:2020-05-04
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