In this paper, novel circuit topologies for near-threshold computing (NTC) are proposed and evaluated. Three separate dynamic differential signaling based logic (DDSL) families are developed in a 130 nm technology to operate at 400 mV and 450 mV. The proposed logic families outperform contemporary CMOS and current-mode logic (CML) circuits implemented for near-threshold. The DDSL families are described as dynamic current-mode logic (DCML), latched DCML (LDCML), and dynamic feedback current-mode logic (DFCML). Simulation and analysis are performed through implementation of boolean functions and a 4×4 bit array multiplier. At a 450 mV supply voltage, the total power of the 4×4 DFCML multiplier is reduced to 0.95× and 0.009×, while the maximum operating frequency is improved by 1.4× and 1.12× as compared to, respectively, a CMOS and CML multiplier. The DCML multiplier consumes 1.48× the power while improving f_max by 1.65× as compared to a CMOS multiplier. A chain of four inverters implemented with the developed dynamic logic families exhibited an energy delay product (EDP) of 0.27× and 0.016× that of, respectively, CMOS and CML implementations. The mean noise margins, also evaluated with a chain of inverters, of DFCML and LDCML are at least 2.5× greater than that of CMOS.

在本文中，提出并评估了用于近阈值计算（NTC）的新型电路拓扑。在130 nm技术中开发了三个独立的基于动态差分信令的逻辑（DDSL）系列，以400 mV和450 mV的电压运行。所提出的逻辑系列的性能优于为接近阈值而实现的现代CMOS和电流模式逻辑（CML）电路。DDSL系列被描述为动态电流模式逻辑（DCML），锁存DCML（LDCML）和动态反馈电流模式逻辑（DFCML）。通过执行布尔函数和4×4位数组乘法器来执行仿真和分析。在450 mV的电源电压下，与CMOS和CML乘法器相比，4×4 DFCML乘法器的总功率降低到0.95×和0.009×，而最大工作频率分别提高了1.4×和1.12×。 。与CMOS乘法器相比，f _max降低了1.65倍。用开发的动态逻辑系列实现的四个反相器链显示出的能量延迟积（EDP）分别是CMOS和CML实现的0.27倍和0.016倍。DFCML和LDCML的平均噪声容限（也由一系列反相器评估）比CMOS至少高2.5倍。