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6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and Its Energy-Aware and High-Throughput Design
IEEE Transactions on Circuits and Systems II: Express Briefs ( IF 4.0 ) Pub Date : 2020-05-01 , DOI: 10.1109/tcsii.2020.2983959
Murilo Perleberg , Vinicius Borges , Vladimir Afonso , Daniel Palomino , Luciano Agostini , Marcelo Porto

This brief presents the Six Wedgelets and six Refinements (6WR), a hardware friendly algorithm targeting the Depth Modeling Mode 1 (DMM-1) encoding tool of the 3D-High Efficiency Video Coding (3D-HEVC) standard. This brief also presents the high-throughput and energy-aware hardware design for the 6WR. The 6WR algorithm reduces 98.5% of the evaluated wedge lets by exploring the edges gradients, with average coding efficiency losses between 1.2% and 2.8%. The hardware design implements the Bresenham algorithm to avoid the use of memory. The synthesis results show that the 6WR architecture can process up to nine views in 3D full HD 1080p videos at 30 frames per second, with a power dissipation of 263.7 mW. When compared with related works, the 6WR architecture reached the highest throughput and the best results of coding efficiency and energy efficiency when the same target throughput is considered.

中文翻译:

6WR:硬件友好的 3D-HEVC DMM-1 算法及其能量感知和高吞吐量设计

本简介介绍了六个楔形和六个细化 (6WR),这是一种硬件友好的算法,针对 3D 高效视频编码 (3D-HEVC) 标准的深度建模模式 1 (DMM-1) 编码工具。本简介还介绍了 6WR 的高吞吐量和能量感知硬件设计。6WR 算法通过探索边缘梯度减少了 98.5% 的评估楔形,平均编码效率损失在 1.2% 到 2.8% 之间。硬件设计实现了 Bresenham 算法,以避免使用内存。综合结果表明,6WR 架构可以以每秒 30 帧的速度处理多达 9 个 3D 全高清 1080p 视频视图,功耗为 263.7 mW。与相关作品相比,
更新日期:2020-05-01
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