All-digital basestation (BS) architectures enable superior spectral efficiency compared to hybrid solutions in massive multi-user MIMO systems. However, supporting large bandwidths with all-digital architectures at mmWave frequencies is challenging as traditional baseband processing would result in excessively high power consumption and large silicon area. The recently-proposed concept of finite-alphabet equalization is able to address both of these issues by using equalization matrices that contain low-resolution entries to lower the power and complexity of high-throughput matrix-vector products in hardware. In this brief, we explore two different finite-alphabet equalization hardware implementations that tightly integrate the memory and processing elements: (i) a parallel array of multiply-accumulate (MAC) units and (ii) a bit-serial processing-in-memory (PIM) architecture. Our all-digital VLSI implementation results in 28nm CMOS show that the bit-serial PIM architecture reduces the area and power consumption up to a factor of $ 2\times $ and $3\times $ , respectively, when compared to a parallel MAC array that operates at the same throughput.

中文翻译：

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具有内存处理功能的毫米波大规模 MU-MIMO 的高带宽空间均衡

与大规模多用户 MIMO 系统中的混合解决方案相比，全数字基站 (BS) 架构可实现卓越的频谱效率。然而，在毫米波频率下通过全数字架构支持大带宽具有挑战性，因为传统的基带处理会导致过高的功耗和大的硅面积。最近提出的有限字母均衡概念能够通过使用包含低分辨率条目的均衡矩阵来降低硬件中高吞吐量矩阵向量乘积的功耗和复杂性，从而解决这两个问题。在这个简介中，我们探索了两种不同的有限字母均衡硬件实现，它们紧密集成了内存和处理元素：(i) 乘法累加 (MAC) 单元的并行阵列和 (ii) 位串行内存处理 (PIM) 架构。我们在 28 纳米 CMOS 中的全数字 VLSI 实施结果表明，位串行 PIM 架构可将面积和功耗降低多达 $ 2\times $ 和 $3\times $ 分别与以相同吞吐量运行的并行 MAC 阵列相比。