Spiking neural networks (SNNs) can achieve lower latency and higher efficiency compared with traditional neural networks if they are implemented in dedicated neuromorphic hardware. In both biological and artificial spiking neuronal systems, synaptic modifications are the main mechanism for learning. Plastic synapses are thus the core component of neuromorphic hardware with on‐chip learning capability. Recently, several research groups have designed hardware architectures for modeling plasticity in SNNs for various applications. Following these research efforts, this paper proposes multiplier‐less digital neuromorphic circuits for two plasticity learning rules: the spike‐driven synaptic plasticity (SDSP) and synaptic strength–based spike timing–dependent plasticity (SSSTDP). The proposed architectures have increased the precision of the plastic synaptic weights and are suitable for spiking neural network architectures with more precise calculations. The proposed models are validated in MATLAB simulations and physical implementations on a field‐programmable gate array (FPGA).

中文翻译：

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高精度SDSP和基于突触强度的STDP的无数字乘法器实现

如果在专用的神经形态硬件中实现，与传统的神经网络相比，尖峰神经网络（SNN）可以实现更低的延迟和更高的效率。在生物和人工加标神经元系统中，突触修饰都是学习的主要机制。因此，塑料突触是具有形态上学习能力的神经形态硬件的核心组件。最近，一些研究小组已经设计了硬件体系结构，以对SNN中的可塑性进行建模以用于各种应用程序。经过这些研究，本文提出了用于两个可塑性学习规则的无乘数数字神经形态电路：峰驱动的突触可塑性（SDSP）和基于突触强度的基于穗时序的可塑性（SSSTDP）。所提出的体系结构提高了塑料突触权重的精度，并适合于通过更精确的计算来增强神经网络体系结构。所提出的模型在MATLAB仿真和现场可编程门阵列（FPGA）的物理实现中得到了验证。