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A one-to-many traffic-oriented mm-wave wireless network-in-package interconnection architecture for multichip computing systems
Sustainable Computing: Informatics and Systems ( IF 3.8 ) Pub Date : 2020-02-15 , DOI: 10.1016/j.suscom.2020.100379
M Meraj Ahmed , Naseef Mansoor , Amlan Ganguly

High Performance Computing (HPC) platforms like blade servers consist of multiple processor chips, which may be multicore CPUs, GPUs, memory modules and other subsystems. In such memory and computation intensive systems one-to-many traffic patterns originate from cache coherency, system-level synchronization mechanisms and other control signals. However, small portions of such traffic can introduce huge local and global congestion, which significantly reduce overall performance and cause energy bottleneck unless low latency transmission is ensured by a one-to-many traffic-aware interconnection architecture. Therefore, these high performance and memory intensive multichip systems require efficient support for one-to-may traffic. Traditional metal-based Network-on-Chip (NoC) interconnection architecture is mostly designed for unicast traffic and therefore not suitable for such one-to-many traffic as it provides high-latency, power-hungry multi-hop paths. To address this issue, we propose the design of a one-to-many traffic-aware Wireless Network-in-Package (WiNiP) architecture by integrating a novel asymmetric wireless interconnection topology, a novel hybrid two-state Medium Access Control (MAC) and flow control. The proposed asymmetric topology, MAC and flow control collaborate with each other to form a low latency, one-to-many traffic-aware WiNiP interconnection architecture and increase system bandwidth with lower energy consumption. Through cycle-accurate simulator we show that the proposed topology reduces average packet latency by 47.92 % and outperforms other interconnection architectures for on and off-chip data transfer for synthetic as well as application-specific traffic patterns.



中文翻译:

用于多芯片计算系统的一对多面向流量的毫米波无线网络封装互连架构

诸如刀片服务器之类的高性能计算(HPC)平台由多个处理器芯片组成,这些芯片可以是多核CPU,GPU,内存模块和其他子系统。在这种存储器和计算密集型系统中,一对多流量模式源自高速缓存一致性,系统级同步机制和其他控制信号。但是,此类流量的一小部分会带来巨大的本地和全局拥塞,除非通过一对多的流量感知互连体系结构确保低延迟传输,否则这将大大降低整体性能并导致能源瓶颈。因此,这些高性能和内存密集型多芯片系统需要对可能的流量进行有效的支持。传统的基于金属的片上网络(NoC)互连体系结构主要是为单播流量设计的,因此不适合此类一对多流量,因为它提供了高延迟,耗电的多跳路径。为了解决这个问题,我们提出了一种通过集成新颖的非对称无线互连拓扑,新颖的混合式两态媒体访问控制(MAC)来设计一对多的具有流量感知能力的无线封装网络(WiNiP)架构的设计。和流量控制。拟议的非对称拓扑,MAC和流控制相互协作以形成低延迟,一对多的流量感知WiNiP互连架构,并以较低的能耗增加系统带宽。通过周期精确的模拟器,我们证明了所提出的拓扑将平均数据包延迟减少了47。

更新日期:2020-02-15
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