The reduction in size of metal oxide semiconductor (MOS) devices results in increase in leakage power dissipation, which occurs due to the short‐channel effects in subthreshold region. Now a day's power dissipation is one of the crucial issues that the modern electronic industry is facing. Fin‐type field‐effect transistor (FinFET) can be proven as a best substitute to reduce leakage power dissipation in logic circuits. Degradation of performance with process variations is of major concern and needs to design FinFET circuits with minimum leakage power dissipation. In this paper, static random‐access memory (SRAM) cell is designed using low power shorted‐gate (SG) FinFETs at 7‐nm technology to minimize leakage power dissipation besides improving other performance parameters like static noise margins (SNMs) and power delay product (PDP) as well. The various parameters are analyzed using butterfly and N‐curve methods. The ASAP7 PDK is used to design SRAM cells using Cadence Virtuoso tool. The simulated results show that FinFET input‐dependent (INDEP) technique reduces the leakage power dissipation by 32.08% and 13.50%, respectively, in read and write conditions of FinFET SRAM cell. The Monte‐Carlo simulation results show the reduction in average power using INDEP approach at ±10% process, voltage and temperature (PVT) variations under 3σ Gaussian distribution of FinFET SRAM cell.

中文翻译：

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7纳米技术的INDEP FinFET SRAM单元设计与分析

金属氧化物半导体（MOS）器件尺寸的减小导致泄漏功耗的增加，这是由于亚阈值区域中的短沟道效应引起的。现在，一天的功耗已成为现代电子行业面临的关键问题之一。鳍式场效应晶体管（FinFET）可以被证明是减少逻辑电路泄漏功耗的最佳替代品。随着工艺变化而导致的性能下降是主要问题，需要设计出具有最小泄漏功耗的FinFET电路。在本文中，静态随机存取存储器（SRAM）单元采用7纳米技术的低功耗短路栅（SG）FinFET设计，可最大程度地降低泄漏功耗，同时改善其他性能参数，例如静态噪声裕量（SNM）和功率延迟产品（PDP）。使用蝶形和N曲线方法分析各种参数。ASAP7 PDK用于使用Cadence Virtuoso工具设计SRAM单元。仿真结果表明，在FinFET SRAM单元的读写条件下，FinFET输入相关（INDEP）技术分别将泄漏功耗降低了32.08％和13.50％。蒙特卡洛仿真结果表明，在FinFET SRAM单元的3σ高斯分布下，采用INDEP方法在±10％的工艺，电压和温度（PVT）变化下，平均功率降低了。在FinFET SRAM单元的读写条件下。蒙特卡洛仿真结果表明，在FinFET SRAM单元的3σ高斯分布下，采用INDEP方法可在±10％的工艺，电压和温度（PVT）变化的情况下降低平均功率。在FinFET SRAM单元的读写条件下。蒙特卡洛仿真结果表明，在FinFET SRAM单元的3σ高斯分布下，采用INDEP方法可在±10％的工艺，电压和温度（PVT）变化的情况下降低平均功率。