Herein, a low‐ripple coarse‐fine digital low‐dropout regulator (D‐LDO) without ringing in the transient state is proposed. Conventional D‐LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D‐LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D‐LDO was fabricated using a 65‐nm CMOS process with an area of 0.0056 μm². The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 μs to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 μA.

中文翻译：

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低纹波粗细数字低压差稳压器，在瞬态不振铃

在此，提出了一种在瞬态不振铃的低纹波粗细数字低压差稳压器（D-LDO）。常规D‐LDO在大负载跃迁下稳定输出电压时会遇到振铃问题，这会增加稳定时间。建议的D‐LDO使用辅助功率级消除了振铃并减少了建立时间，该功率级将其输出电流调整为瞬态状态下的负载电流。它也可以使用具有完整比较信号的比较器来实现低输出纹波电压。所提出的d-LDO是使用65纳米CMOS具有0.0056微米的面积工艺制造²。当负载电流在20 ns的边沿时间内从10 mA变为100 mA时，下冲和过冲分别为47 mV和23 mV。稳定时间从2.1μs降至130 ns，纹波电压为3 mV，静态电流为75μA。