ABSTRACT This paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype’s measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm2. The energy required per conversion step is 0.4 pJ/conv.

中文翻译：

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5MHz 带宽 78.1dB SNDR 2-2 MASH Delta-Sigma 调制器

摘要 本文介绍了一种使用 0.18 µm 互补金属氧化物半导体 (CMOS) 工艺制造的 4 位、2–2 多级噪声整形 (MASH) Δ-Σ 调制器 (DSM)。DSM 是使用具有前馈 (CIFF) 结构的级联积分器设计的。第一个积分器旨在使用开关电阻积分器代替传统的开关电容方法来降低系统前端电路的负载效应。CIFF 结构需要一个有源加法器，一般用高带宽高摆幅放大器来实现。在本文中，取消了有源加法器，并在 MASH DSM 中实现了无加法器积分器。DSM 原型的过采样率 (OSR) 为 16，采样频率为 160 MHz。原型机测得的信噪比 (SNR) 为 82。对于 5 MHz 的信号带宽，4 dB 和信噪加失真比 (SNDR) 为 78.1 dB。在 1.8 V 电源电压下测得的总功耗为 26 mW，芯片核心尺寸为 0.67 mm2。每个转换步骤所需的能量为 0.4 pJ/conv。