Estimating the power consumption and computational complexity of various digital signal processing (DSP) algorithms used in wireless communications systems is critical to assess the feasibility of implementing such algorithms in hardware, and for designing energy-constrained communications systems. Therefore, this paper presents a novel approach, based on practical system measurements using field programmable gate array (FPGA) and application-specific integrated circuit (ASIC), to evaluate the power consumption and the associated computational complexity of the most common mathematical operations performed within various DSP algorithms. Using the proposed approach, a new metric is developed for mapping the computational complexity to the computational power consumed by the mathematical operation in wireless transceivers. This allows combining the commonly used computational complexity metrics that are typically computed for each mathematical operation separately. Consequently, a single unified metric can be used to describe the entire algorithm. Therefore, the comparison and trade-offs between different algorithms become easier and more informative. The developed approach is used to evaluate the computational power of several DSP algorithms used in wireless communications systems, and perform thorough computational complexity comparisons. The obtained results reveal that computational complexity comparisons using different mathematical operations can be highly misleading in several scenarios. The power consumption evaluation of the considered DSP algorithms show that some algorithms may require a prohibitively high power, which makes such algorithms unsuitable for power-constrained wireless communications systems. The results also show that the proposed methodology can be adopted for various hardware implementation, however, some calibration might be required based on the adopted platform.

中文翻译：

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能源受限的无线通信系统的计算能力评估

估计在无线通信系统中使用的各种数字信号处理（DSP）算法的功耗和计算复杂度，对于评估在硬件中实施此类算法的可行性以及设计能量受限的通信系统至关重要。因此，本文提出了一种新颖的方法，该方法基于使用现场可编程门阵列（FPGA）和专用集成电路（ASIC）进行的实际系统测量，以评估功耗和相关的计算复杂性，这些运算和计算复杂度是在该过程中执行的。各种DSP算法。使用提出的方法，开发了一种新的度量标准，用于将计算复杂度映射到无线收发器中数学运算所消耗的计算能力。这允许组合通常为每个数学运算分别计算的常用计算复杂性度量。因此，可以使用一个统一的度量标准来描述整个算法。因此，不同算法之间的比较和折衷变得更容易且更有意义。开发的方法用于评估无线通信系统中使用的几种DSP算法的计算能力，并进行全面的计算复杂度比较。获得的结果表明，在几种情况下，使用不同数学运算的计算复杂度比较可能会产生极大的误导。对已考虑的DSP算法的功耗评估表明，某些算法可能会要求过高的功率，这使得这种算法不适用于功率受限的无线通信系统。结果还表明，所提出的方法可以用于各种硬件实现，但是，基于所采用的平台，可能需要进行一些校准。