One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists, which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of LER is presented and analyzed for yield loss induced by open/short failures, cut mask defects, enhanced time dependent dielectrics breakdown (TDDB) failures for metal wires with different geometries, electro-migration (EM) impacts from the presence of LER on SRAM bitlines, and finally, LER impacts on functional errors. The model will be evaluated on single and double patterned designs with metal pitches of 24 and 28 nanometers. We show experimental results and give specific criteria in which LER thresholds can be relaxed without negatively impacting yield and path delay. This is a critical issue as higher LER tolerance allows exponential increase in throughput and thus reduces cost of fabrication.

中文翻译：

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后端线边缘粗糙度的设计影响

EUV 光刻的主要问题之一是光刻胶上的线边缘粗糙度 (LER)，这会显着影响亚 30 nm 间距的良率。在这项工作中，提出了一个 LER 分析模型，并分析了由开路/短路故障、切割掩模缺陷、不同几何形状的金属线的增强时间相关介电击穿 (TDDB) 故障、电迁移 (EM) 影响引起的良率损失从 SRAM 位线上 LER 的存在来看，最后，LER 对功能错误的影响。该模型将在金属间距为 24 和 28 纳米的单图案和双图案设计上进行评估。我们展示了实验结果并给出了具体的标准，在这些标准中，可以放宽 LER 阈值而不会对产量和路径延迟产生负面影响。