A 30Gbps power-efficient equalizer including an adaptive loop combined with a direct current offset cancellation (DCOC) loop is presented in this paper. Based on spectrum balanced technique, the adaptive loop applies signal strength indication (SSI) circuit to detect the low and high frequency power of equalized signal. After that, peaking gain of equalizer is adjusted according to detection value of SSI circuits. With the help of operation amplifier and trans-conductance amplifier, the proposed DCOC loop decreases the mismatch error. By applying inductive peaking and RC-degeneration technique, the continuous time linear equalizer (CTLE) compensates for channel insert loss in equalizer. A double-f_T cell with inductive peaking technique is utilized to expand the bandwidth. To reduce effect of parasitic capacitor from output buffer, equalized signal is reshaped by three-stage cascaded limiting amplifier. Benefiting from excellent impedance matching by employing micro-strip and peaking inductor in terminal, the maximum channel loss equalized at 14 ​GHz is −18dB. The maximum reflection loss of Sdd11 and Sdd22 measured at 42 ​GHz and below are -9dB. Peak-peak jitter of 11.33ps is measured at 30Gbps after equalization. Meanwhile, only 53 ​mW power dissipation is consumed with a power supply of 1.8 ​V. Fabricated in 0.13 ​ ​μm SiGe BiCMOS technology, this chip only occupies active area of 0.32 ​mm².

本文提出了一种具有自适应环路和直流失调（DCOC）环路相结合的30Gbps节能均衡器。自适应环路基于频谱平衡技术，应用信号强度指示（SSI）电路来检测均衡信号的低频和高频功率。之后，根据SSI电路的检测值调整均衡器的峰值增益。借助运算放大器和跨导放大器，建议的DCOC环路可降低失配误差。通过应用电感峰值和RC退化技术，连续时间线性均衡器（CTLE）补偿了均衡器中的通道插入损耗。一个双˚F _ŧ利用具有感应峰值技术的单元来扩展带宽。为了减少来自输出缓冲器的寄生电容器的影响，均衡的信号通过三级级联限制放大器进行整形。通过在端子中采用微带和峰值电感器，可实现出色的阻抗匹配，在14 GHz时均衡的最大通道损耗为-18dB。在42 GHz及以下测量的Sdd11和Sdd22的最大反射损耗为-9dB。均衡后在30Gbps时测得的峰值抖动为11.33ps。同时，使用1.8 V电源仅消耗53 mW的功耗。该芯片采用0.13μmSiGe BiCMOS技术制造，仅占据0.32 mm ^2的有效面积。