In this paper, a new method for multiplying two n-trit numbers using CNFET and ternary logic is introduced. The carry resulted from the ternary multiplier never takes the value of two and is always zero or one. In this paper, this feature of the carry is used to construct two novel capacitive and transistor structures for reducing the partial product tree. These structures simultaneously improve the power consumption and latency, and the higher is the number of the trits of the two multiplied numbers, the increase in this improvement will be more. In this paper, on average, the proposed capacitive structure improves power consumption, latency and PDP as much as 26.72%, 9.74% and 33.8% respectively compared to the original structure. This improvement for the proposed transistor structure will be changed to 26.67%, 8.77% and 33.04% respectively. The reason for the lower improvement in the transistor structure is the overhead in this structure, which will be examined.

本文提出了一种将两个n相乘的新方法介绍了使用CNFET和三元逻辑的Trit数。三元乘法器产生的进位从不取值为2，并且始终为零或一。在本文中，进位的这一特征用于构造两个新颖的电容和晶体管结构，以减少部分乘积树。这些结构同时改善了功耗和等待时间，并且两个相乘数的三叉戟数目越多，这种改善的增加就越大。在本文中，与原始结构相比，拟议的电容结构平均将功耗，延迟和PDP分别提高了26.72％，9.74％和33.8％。提议的晶体管结构的改进将分别更改为26.67％，8.77％和33.04％。