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Design of low power Teager Energy Operator circuit for Sleep Spindle and K-Complex extraction
Microelectronics Journal ( IF 1.9 ) Pub Date : 2020-04-14 , DOI: 10.1016/j.mejo.2020.104785
Sumaiyah I. Khan , Maha S. Diab , Soliman A. Mahmoud

This work presents an ultra-low-power subthreshold four-quadrant multiplier and a subthreshold programmable second order Butterworth Gm-C Low-Pass Filter (LPF) targeted for realizing optimized Teager Energy Operator (TEO). The ultra-low-power and low voltage strategies involve weak inversion biasing, reducing multiplier power consumption and eliminating summation block from the general TEO algorithm. The circuits dynamic range and bandwidths are designed for the Sleep Spindle (SS) and K-Complex (K–C) frequency range of the Electroencephalogram (EEG) signal. The ideal TEO response is initially modelled using MATLAB and Simulink in order to verify the theoretical basis. The final circuits are then simulated using Analog Devices’ LTSpice MOSFET models of 90 ​nm BSIM4 version 4.3 level 54. The multiplier simulations prove a dynamic range of ±40 ​mV ​at a supply voltage of 0.6 ​V with a linearity error of 2.6%. The Total Harmonic Distortion (THD) at 16 ​Hz for an input of 20 ​mV AC signal and another fixed input at 1 ​mV is 0.2159%. The LPF is operated at ± 0.6 ​V with a low static power consumption of 1.95 ​nW. Programmability of the LPF has control over both gain and bandwidth, offering the designer a choice over the group delay. The overall transient response of the TEO demonstrates its amplitude and frequency tracking capability in accordance with its theoretical performance. The final TEO circuit achieves the lowest static power consumption reported in the sleep research literature of 53.59 ​nW. This makes the proposed TEO circuit, the lowest power consuming joint EEG waveform detecting Application Specific Integrated Circuit (ASIC).



中文翻译:

用于睡眠主轴和K复杂提取的低功耗Teager能量运算器电路的设计

这项工作提出了一个超低功耗亚阈值四象限乘法器和一个亚阈值可编程二阶Butterworth Gm-C低通滤波器(LPF),旨在实现优化的Teager能源运营商(TEO)。超低功耗和低压策略涉及弱反相偏置,降低乘法器功耗以及从通用TEO算法中消除求和模块。电路的动态范围和带宽设计用于脑电图(EEG)信号的睡眠主轴(SS)和K复杂(K–C)频率范围。为了验证理论基础,最初使用MATLAB和Simulink对理想的TEO响应进行了建模。然后使用ADI公司的90nm BSIM4版本4.3等级54的LTSpice MOSFET模型对最终电路进行仿真。乘法器仿真证明在0.6 V的电源电压下动态范围为±40 mV,线性误差为2.6%。对于20 mV交流信号输入和另一个1 mV固定输入,在16 Hz处的总谐波失真(THD)为0.2159%。LPF的工作电压为±0.6 V,静态功耗为1.95 nW。LPF的可编程性可同时控制增益和带宽,从而为设计人员提供了群延迟选择。TEO的整体瞬态响应根据其理论性能证明了其幅度和频率跟踪能力。最终的TEO电路实现了睡眠研究文献中报告的最低静态功耗53.59 nW。这使得拟议的TEO电路,

更新日期:2020-04-14
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