Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported functionality. However, GC-eDRAM requires periodic refresh cycles to maintain its data due to its dynamic storage mechanism. The refresh operation is typically handled at a memory controller level, resulting in an energy overhead and limited memory availability. In this paper, we propose a new approach for the realization of the refresh operation using an internal refresh mechanism, which supports an efficient row-wise refresh operation within a single clock cycle, providing 100% write access availability at a reduced refresh latency and power. An 8 kbit GC-eDRAM array with integrated internal refresh and replica bit-line was implemented, demonstrating up-to 30% reduced refresh latency and 65% reduced read energy at a low cost of 2.4% array area overhead, compared to a conventional GC-eDRAM array without internal refresh capabilities.

嵌入式存储器主要由静态随机存取存储器（SRAM）实现，它支配着集成电路的面积和功率。增益单元嵌入式DRAM（GC-eDRAM）由于具有高密度，低功耗和两端口功能而成为SRAM的替代产品。但是，由于其动态存储机制，GC-eDRAM需要定期刷新周期以维护其数据。刷新操作通常在内存控制器级别进行，从而导致能源开销和有限的内存可用性。在本文中，我们提出了一种使用内部刷新机制实现刷新操作的新方法，该方法支持在单个时钟周期内进行有效的逐行刷新操作，以降低的刷新延迟和功耗提供100％的写访问可用性。