Thin film transistors (TFTs) with lateral channels are limited in current density due to the design rule. For many applications with improved integration, the introduction of vertical channels reduces channel lengths while increasing current density per unit surface area. In previous works, vertical TFTs have been designed and manufactured using low-temperature polycrystalline silicon technology (T ≤ 600 °C), with a solid phase crystallization (SPC) based process. In this case, the introduction of an insulating layer between source and drain films has resulted in a significant improvement in the electrical characteristics, mainly in the On/Off state current (I_on/I_off) ratio. However, the active layer is deposited on the sidewalls obtained by plasma etching, and the etching process results in morphological defects on the sidewalls that adversely affect the electrical characteristics. The purpose of this paper is to understand the origin and effects of these defects using different models. Thus, the transfer characteristics are analyzed in detail, with Suzuki method to calculate the density of states, while subthreshold slope method and Grünewald method are adopted to verify the Suzuki method for the deep and shallow trap densities, respectively. These methods provide an approach for DOS calculation independent of temperature-related measurement.

由于设计规则，具有横向沟道的薄膜晶体管（TFT）的电流密度受到限制。对于集成度得到改善的许多应用，引入垂直沟道可减小沟道长度，同时增加每单位表面积的电流密度。在以前的工作中，垂直TFT是使用低温多晶硅技术（T≤600°C）通过固相结晶（SPC）工艺设计和制造的。在这种情况下，在源极膜和漏极膜之间引入绝缘层已导致电气特性的显着改善，主要是在开/关状态电流（I _on / I _off）比率。然而，活性层沉积在通过等离子体蚀刻获得的侧壁上，并且蚀刻工艺导致侧壁上的形态缺陷，这不利地影响电特性。本文的目的是使用不同的模型来了解这些缺陷的起源和影响。因此，对传输特性进行了详细的分析，使用Suzuki方法计算状态密度，而分别采用亚阈值斜率方法和Grünewald方法来验证Suzuki方法的深陷阱密度和浅陷阱密度。这些方法提供了一种独立于温度相关测量的DOS计算方法。