In this paper we present a simulation study of a novel Double-Gate (DG) Ferroelectric FET (Fe-FET) architecture, exhibiting a subthreshold swing well below 60 mV/dec with a hysteresis-free behavior. The new device topology is based on the interposition of a floating gate between the ferroelectric layer and the gate oxide. The floating gate can be extended above the source and drain regions, so that its capacitance can be suitably optimized to ensure device stability. We found that both the overlap capacitance and quantum confinement are beneficial for the amplification factor. The $I_{\mathrm{ON}}$ improvement over the standard DG MOSFET turns out to be 23.7×, with no degradation of the intrinsic transit time.

在本文中，我们对新型双栅极（DG）铁电FET（Fe-FET）架构进行了仿真研究，其亚阈值摆幅远低于60 mV / dec，并且没有磁滞现象。新的器件拓扑基于铁电层和栅极氧化物之间的浮置栅极。浮栅可以在源极和漏极区域上方延伸，因此可以适当优化其电容以确保器件的稳定性。我们发现，重叠电容和量子限制都有利于放大倍数。的${\mathrm{一世}}_{\mathrm{上}}$ 与标准DG MOSFET相比，改进后的结果是23.7倍，而本征传输时间没有降低。