For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm² SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD = 0.8 V and a reduction of minimum operating voltage V_min by 60 mV (up to 92 mV with speed penalty) at 6σ w.r.t. planar SRAMs.

我们首次提出了一种3D单片SRAM架构，该架构具有用于顶层晶体管的本地背板，从而实现了本地背偏置辅助技术，而不会造成面积损失，并且能够在单个晶体管上路由两个额外的按行信号背飞机。实验数据是从14 nm平面全耗尽型绝缘体上硅（FDSOI）0.078 µm ² SRAM单元中提取的，以便正确地对3D顶层单元进行建模。进行BTI测量以确保建议的辅助功能不会提供额外的压力。仿真表明，该技术可在VDD = 0.8 V时将位线电容减小7％，将读/写访问时间缩短12％/ 50％，并将最低工作电压V _min降低60 mV（速度下降时最高可达92 mV）。平面SRAM时为6σ。