We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates to obtain a better power-performance metric for logic applications for advanced sub-5 nm technology nodes, in comparison to finFETs. In addition, vertical NW/NS GAA FETs appear particularly attractive for enabling highly dense memory cells such as SRAMs (with improved read and write stability), and as the selector devices for ultra-scaled MRAMs with lower energy consumption values. These cells can be manufactured by a cost-effective, co-integration scheme with a triple-gate finFET or a lateral NW/NS GAA FET high-performance logic platform for increased on-chip memory content.

与之相比，我们报告了垂直堆叠的横向纳米线（NW）/纳米片（NS）全方位栅（GAA）FET器件，有望为先进的5纳米以下技术节点的逻辑应用获得更好的功率性能指标到finFET。此外，垂直NW / NS GAA FET看起来特别吸引人，因为它可以实现高密度存储单元（如SRAM）（具有提高的读写稳定性），并具有较低的能耗值，可作为超大规模MRAM的选择器。这些单元可以通过具有成本效益的，与三栅极finFET或横向NW / NS GAA FET高性能逻辑平台的共集成方案来制造，以增加片上存储器的内容。