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Dynamic partial reconfiguration enchanced with security system for reduced area and low power consumption
Microprocessors and Microsystems ( IF 1.9 ) Pub Date : 2020-03-14 , DOI: 10.1016/j.micpro.2020.103088
R. Saravana Ram , M. Lordwin Cecil Prabhaker , K. Suresh , Kamalraj Subramaniam , M. Venkatesan

Field-programmable gate arrays (FPGAs) have travelled far from just being utilized as glue logic to an entire system solution. This is mostly due to their generalized re-configurable nature, lower non-recurring engineering (NRE) expense, and also fast time to market. Owing to the reconfigurable nature of FPGA, a new field called reconfigurable computing that can change the circuit configuration after hardware production came into existence. Application of re-configurable computing for self-adaptive hardware allows hardware to get adapt to various environmental conditions and different needs by swapping or loading disparate computational modules. This work proposes an effectual design methodology (enhanced DPR security system (EDPRSS)) utilized to execute high performance FPGA device in respect of low power consumption along with security for the area reduction. In the proposed technique, hash code generation (HCG) and encryption hardware accelerators can well be dynamically produced on FPGA utilizing partial re-configuration as stated by the application requisites. The system is competent to swap in or swap out the equivalent hardware accelerator during run time, which in turn diminishes the power and area. Here, 2 re-configurable partitions are produced for encryption and also HCG algorithm. Experiential outcomes proved that the proposed technique proffers better performance when contrasted to the other conventional systems.



中文翻译:

通过安全系统增强了动态部分重新配置的功能,从而减少了面积并降低了功耗

现场可编程门阵列(FPGA)远不只是用作胶合逻辑到整个系统解决方案。这主要是由于它们具有通用的可重新配置特性,较低的非经常性工程(NRE)费用以及快速的上市时间。由于FPGA具有可重配置的特性,因此一个称为可重配置计算的新领域可以在硬件生产出现后改变电路配置。自适应硬件的可重新配置计算的应用允许硬件通过交换或加载不同的计算模块来适应各种环境条件和不同需求。这项工作提出了一种有效的设计方法(增强的DPR安全系统(EDPRSS)),该方法可用于在降低功耗的同时降低功耗并执行高性能FPGA器件。在所提出的技术中,如应用程序要求所述,可以利用部分重新配置在FPGA上动态地动态生成哈希码生成(HCG)和加密硬件加速器。该系统可以在运行时更换或更换等效的硬件加速器,从而减少了功率和面积。在此,将生成2个可重新配置的分区用于加密以及HCG算法。实验结果证明,与其他常规系统相比,所提出的技术具有更好的性能。哈希码生成(HCG)和加密硬件加速器可以很好地在FPGA上动态生成,如应用程序要求所述,可以使用部分重新配置。该系统可以在运行时更换或更换等效的硬件加速器,从而减少了功率和面积。在此,将生成2个可重新配置的分区用于加密以及HCG算法。实验结果证明,与其他常规系统相比,所提出的技术具有更好的性能。哈希码生成(HCG)和加密硬件加速器可以很好地在FPGA上动态生成,如应用程序要求所述,可以使用部分重新配置。该系统可以在运行时更换或更换等效的硬件加速器,从而减少了功率和面积。在此,将生成2个可重新配置的分区用于加密以及HCG算法。实验结果证明,与其他常规系统相比,所提出的技术具有更好的性能。产生2个可重新配置的分区用于加密以及HCG算法。实验结果证明,与其他常规系统相比,所提出的技术具有更好的性能。产生2个可重新配置的分区用于加密以及HCG算法。实验结果证明,与其他常规系统相比,所提出的技术具有更好的性能。

更新日期:2020-03-14
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