Since their appearance, programmable logic controllers (PLCs) are massively and predominantly used as the central controller in automation systems. Unfortunately, due to the poor performance of the majority of these devices, the typical role of PLCs in automation systems becomes restricted to a simple controller, since applications with more sophisticated computational requirements tend to be handled by external processing units along with the PLCs. To solve this issue, this work improves novel architecture proposals based on data flow machines, circuit simulation theory, and the memoization technique to achieve a performance boost based on the scan time reduction. Along with the architectural improvements, this paper evaluates the impact of different execution units’ types and quantities in a cycle-accurate simulator (CAS) that was specially developed to simulate the PLC cores. Furthermore, in order to perform a robust and complete evaluation, the silicon areas of the simulated architectures are calculated using the McPAT framework to establish the performance/area relationship of the simulated cores. Evaluation results show best scan time reductions of up to 68% for cores with single execution units and up to 89% for cores with multiple execution units, as well as a best-case of 50% scan time reduction with an acceptable impact on the silicon area. Lastly, the evaluation of the results of the proposed improved cores with multiple execution units shows that they outperform the theoretical performance limit of multiple execution units based on Amdahl’s law up to 4 execution units.

自从出现以来，可编程逻辑控制器（PLC）被广泛用作自动化系统的中央控制器。不幸的是，由于大多数此类设备的性能较差，PLC在自动化系统中的典型作用已被限制为简单的控制器，因为具有更复杂的计算要求的应用程序往往由外部处理单元与PLC一起处理。为了解决这个问题，这项工作改进了基于数据流机，电路仿真理论和记忆技术的新颖架构建议，以基于减少扫描时间来提高性能。随着体系结构的改进，本文在专门为模拟PLC内核而开发的精确周期仿真器（CAS）中评估了不同执行单元的类型和数量的影响。此外，为了执行健壮和完整的评估，使用McPAT框架计算仿真架构的硅面积，以建立仿真核心的性能/面积关系。评估结果显示，对于具有单个执行单元的内核，最佳扫描时间最多可减少68％，对于具有多个执行单元的内核，最多可减少89％，并且在最佳情况下可以将扫描时间减少50％，并且对硅片的影响可以接受区。最后，