Specialized power-down circuitry can switch off an analog circuit when not required for system operation. When interconnecting sub-circuits with power-down functionality, new design errors, i.e. short-circuit paths, floating nodes and asymmetrical voltages at matched structures, may emerge in the power-down mode of the resulting hierarchical circuit. This paper presents a new method for the verification of the power-down mode of hierarchical analog circuits. In contrast to flat verification approaches, intermediate results are reused during computation. The obtained verification results can be used to revise and correct detected errors. Experimental results for a high input impedance differential amplifier are given.

不需要系统操作时，专用的掉电电路可以关闭模​​拟电路。当将具有断电功能的子电路互连时，新的设计错误（即短路路径，浮动节点和匹配结构处的不对称电压）可能会在最终分层电路的断电模式下出现。本文提出了一种验证分层模拟电路掉电模式的新方法。与平面验证方法相比，中间结果在计算过程中被重用。所获得的验证结果可用于修改和纠正检测到的错误。给出了高输入阻抗差分放大器的实验结果。