The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (CORDIC) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, CORDIC needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 CORDIC algorithm takes n/4 iteration as compared to n iteration of the radix-2 CORDIC algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex−7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

快速傅立叶变换（FFT）是一种广泛用于实时数字信号处理中计算离散傅立叶变换（DFT）的算法。对于任何实时应用程序来说，以更少的资源获得高性能是非常理想的。我们提出的工作提出了基于改进的前馈双路径延迟换向器（DDC）架构的，基数为2的频率抽取（R2DIF）FFT算法在FPGA器件上的实现。需要复杂的乘法器来执行复杂的旋转因子的乘法运算以及需要大容量的存储器来存储旋转因子，这是FFT实现的主要考虑因素。提议工作旨在解决这些问题。在这项工作中，提出了一种基于基数的高性能基数16坐标旋转数字计算机（CORDIC）算法来执行复杂的旋转因子乘法。进一步，CORDIC仅需要旋转角度即可执行复杂的乘法运算，从而减少了存储大的存储器来存储旋转因子的需求。计算的总旋转n位精度，我们提出的基数16 CORDIC算法需要进行n / 4次迭代，而基数2 CORDIC算法则需要进行n次迭代。我们提出的基数2频率抽取（R2DIF）算法的体系结构是在Virtex-7系列FPGA上实现的。此外，在我们提出的FFT实现和其他最近提出的FFT实现之间进行了详细的比较。实验结果表明，与最近提出的实现相比，提出的实现具有更少的延迟和硬件利用率。