Noise-interference is one of the major concerns in low-power VLSI circuits. Due to power supply downscaling, these circuits have an extremely limited noise margin that is inadequate for dealing with intrinsic and extrinsic noise. The MRF-based design has been accepted as a highly effective method for designing noise-tolerant low-power circuits. However, the MRF-based circuits suffer from a complex structure and the methods which tried to simplify the structure always sacrificed the noise immunity for hardware simplicity. In this paper, we propose a novel MRF-based method for designing efficient and reliable low-power VLSI circuits. For the first time, an innovative reliability boosting mechanism based on maximum conditional correct probability is incorporated into an efficient MRF-based structure which leads to highly reliable circuits with considerably low cost, delay, and power consumption. The proposed method demonstrates the best performance among all of the previously reported methods. Moreover, the Monte Carlo simulations confirm that the proposed method can preserve its superior noise immunity even under serious process, voltage, and temperature variations.

噪声干扰是低功耗VLSI电路中的主要问题之一。由于电源缩减，这些电路的噪声容限非常有限，不足以处理本征噪声和非本征噪声。基于MRF的设计已被接受为设计耐噪声的低功率电路的高效方法。然而，基于MRF的电路具有复杂的结构，并且试图简化结构的方法总是为了硬件简化而牺牲了抗扰性。在本文中，我们提出了一种新颖的基于MRF的方法来设计高效，可靠的低功耗VLSI电路。首次，一种基于最大条件正确概率的创新可靠性增强机制被并入了高效的基于MRF的结构中，该结构可带来具有相当低的成本，延迟和功耗的高度可靠的电路。所提出的方法在所有先前报告的方法中均表现出最佳性能。此外，蒙特卡洛模拟证实了该方法即使在严重的过程，电压和温度变化下也可以保持其优异的抗噪性。