Due to the nature of applications such as critical infrastructure and the Internet of Things etc. side channel analysis attacks are becoming a serious threat. Side channel analysis attacks take advantage from the fact that the behaviour of crypto implementations can be observed and provides hints that simplify revealing keys. A new type of SCA is the so called horizontal differential SCA. In this paper we investigate two different approaches to increase the inherent resistance of our hardware accelerator for the kP operation. The first approach aims at reducing the impact of the addressing in our design by realizing a regular schedule of the addressing. In the second approach, we investigated how the formula used to implement the multiplication of GF(2ⁿ)-elements influences the results of horizontal DPA attacks against a Montgomery kP-implementation. We implemented 5 designs with different partial multipliers, i.e. based on different multiplication formulae. We used two different technologies, i.e. a 130 and a 250 nm technology, to simulate power traces for our analysis. We show that the implemented multiplication formula influences the success of horizontal attacks significantly. The combination of these two approaches leads to the most resistant design. For the 250 nm technology only 2 key candidates could be revealed with a correctness of about 70% which is a huge improvement given the fact that for the original design 7 key candidates achieved a correctness of more than 90%. For our 130 nm technology no key candidate was revealed with a correctness of more than 60%.

由于关键基础设施和物联网等应用程序的性质，侧信道分析攻击正成为严重的威胁。边信道分析攻击利用了以下事实的优势：可以观察到加密实现的行为，并提供简化揭示密钥的提示。一种新型的SCA是所谓的水平差分SCA。在本文中，我们研究了两种不同的方法来增加kP操作的硬件加速器的固有电阻。第一种方法旨在通过实现定期的编址时间表来减少编址在我们设计中的影响。在第二种方法中，我们研究了公式如何用于实现GF（2 ⁿ）的乘法元素影响对蒙哥马利kP的水平DPA攻击的结果-实现。我们实现了5个具有不同部分乘数的设计，即基于不同的乘法公式。我们使用两种不同的技术（即130和250 nm技术）来模拟功率迹线以进行分析。我们表明，已实现的乘法公式会显着影响水平攻击的成功。这两种方法的结合导致了最耐久的设计。对于250 nm技术，只有2个关键候选对象的正确性约为70％，这是一个巨大的改进，因为对于原始设计，有7个关键候选对象的正确率超过90％。对于我们的130 nm技术，没有发现正确率超过60％的关键候选对象。