Quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted by the Consultative Committee for Space Data Systems (CCSDS) as the recommended standard for onboard channel coding in Near-Earth and Deep-Space communications. Encoder architectures proposed so far are not efficient for high-throughput hardware implementations targeting the specific CCSDS codes. In this article, we introduce a novel architecture for the multiplication of a dense quasi-cyclic (QC) matrix with a bit vector, which is the fundamental operation of QC-LDPC encoding. The architecture leverages the inherent parallelism of the QC structure by concurrently processing multiple bits, according to an optimized scheduling. Based on this architecture, we propose efficient encoders for CCSDS codes, according to all the applicable low-density parity-check (LDPC) code encoding methods. Moreover, in the special case of the code for Near-Earth communications, we also introduce a preprocessing algorithm to efficiently handle the challenges arising from the generator’s matrix circulant size (511 bits). The proposed architectures have been implemented in various field-programmable gate array (FPGA) technologies and validated in Zynq UltraScale+ multiprocessor system-on-chip (MPSoC), achieving a significant speedup compared with previous approaches, while at the same time keeping resource utilization low.

中文翻译：

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多千兆位 CCSDS LDPC 编码器的高效架构

空间数据系统咨询委员会 (CCSDS) 已采用准循环低密度奇偶校验 (QC-LDPC) 码作为近地和深空通信中的机载信道编码的推荐标准。迄今为止提出的编码器架构对于针对特定 CCSDS 代码的高吞吐量硬件实现效率不高。在本文中，我们介绍了一种用于将密集准循环 (QC) 矩阵与位向量相乘的新架构，这是 QC-LDPC 编码的基本操作。该架构通过根据优化调度同时处理多个位来利用 QC 结构的固有并行性。基于这种架构，我们为 CCSDS 代码提出了高效的编码器，根据所有适用的低密度奇偶校验 (LDPC) 代码编码方法。此外，在近地通信代码的特殊情况下，我们还引入了一种预处理算法，以有效处理由发生器矩阵循环大小（511 位）引起的挑战。所提出的架构已在各种现场可编程门阵列 (FPGA) 技术中实现并在 Zynq UltraScale+ 多处理器片上系统 (MPSoC) 中得到验证，与之前的方法相比实现了显着的加速，同时保持低资源利用率.