Low-power system-on-a-chip (SoC) with multiple voltage domains often adopts voltage scaling approaches to optimize power usage while maintaining enough performance. Voltage regulators having flexible output configurability, fast transient response, and high-power noise rejection ability are indispensable for this application scenario. A low-dropout (LDO) regulator was proposed in this article to convert an input of 1.9–1.1 V to an output of 1.1–0.2 V with a 10-mV tuning resolution by raising the concept of programmable recursively divide-by-two resistor array (PRDTRA). A high gain-bandwidth main regulation loop of the proposed LDO regulator was accompanied by a transient acceleration (TA) path and a unity power noise gain generator to achieve a 28-mV output variation during 0–100-mA load transient test while keeping a 60-dB power supply rejection ratio (PSRR) over a frequency band of 0–1 MHz. Performance evaluations show the performance superiority of the proposed LDO regulator.

中文翻译：

---

高性能 LDO 稳压器支持采用电压调节方法的低功耗 SoC

具有多个电压域的低功耗片上系统 (SoC) 通常采用电压缩放方法来优化功耗，同时保持足够的性能。具有灵活输出可配置性、快速瞬态响应和大功率噪声抑制能力的稳压器对于这种应用场景是必不可少的。本文提出了一种低压差 (LDO) 稳压器，通过提出可编程递归二分频电阻器的概念，以 10mV 的调谐分辨率将 1.9-1.1V 的输入转换为 1.1-0.2V 的输出阵列 (PRDTRA)。建议的 LDO 稳压器的高增益带宽主调节环路伴随着瞬态加速 (TA) 路径和单位功率噪声增益发生器，以在 0–100 mA 负载瞬态测试期间实现 28 mV 输出变化，同时保持60-dB 电源抑制比 (PSRR) 在 0–1 MHz 频带内。性能评估显示了所提议的 LDO 稳压器的性能优势。