A two-stage successive approximation register analog-to-digital converter (ADC) is reported. The power consumption is reduced by a technique, which combines the charge sharing passive residue transfer and the $V_{\mathrm {cm}}$ -based switching methods. It is shown this technique reduces the transfer and the fine stage switching energy by 75%. In addition, the noise, the linearity, and the settling time are analyzed. To verify the performance throughout PVT variations, the full circuit is simulated in a 180-nm CMOS process. According to the simulation results, the ADC achieves a signal-to-noise and distortion ratio of 51.27 dB and a spurious-free dynamic range of 64.36 dB. The total power consumption of the calibration-free ADC is 2.99 mW, and the achieved figure of merit is 143 fJ/conversion-step, at a sampling rate of 70 MS/s.

中文翻译：

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具有无源残留转移的 9 位 70-MS/s 两级 SAR ADC

报告了一种两级逐次逼近寄存器模数转换器 (ADC)。通过结合电荷共享被动残留转移和基于 $V_{\mathrm {cm}}$ 的开关方法的技术降低了功耗。结果表明，该技术将转移和精细级开关能量降低了 75%。此外，还分析了噪声、线性度和稳定时间。为了验证整个 PVT 变化的性能，在 180-nm CMOS 工艺中模拟了整个电路。根据仿真结果，ADC 实现了 51.27 dB 的信噪比和失真比和 64.36 dB 的无杂散动态范围。免校准 ADC 的总功耗为 2.99 mW，实现的品质因数为 143 fJ/转换步长，采样率为 70 MS/s。