This article presents the theoretical analysis of passive charge sharing-based segmented successive-approximation-register (SAR) analog-to-digital converter (ADC), where the precise reference source in a capacitive digital-to-analog converter (CDAC) is replaced by a capacitor that is β\beta times larger than its bit capacitor and precharged to the reference level, known as a reference charge reservoir (RCR). A segmented SAR-ADC uses a coarse SAR-ADC to compute some most significant bits (MSBs). Four methods, namely aligned switching (AS) with bitwise RCRs, AS with a subsample-wise RCR, detect-and-skip aligned switching (DAS-AS) with bitwise RCRs, and DAS-AS with a subsample-wise RCR are introduced for setting fine MSBs. Closed-form analytic expressions of the reference error due to the finite reference capacitance are derived and validated by behavioral modeling and circuit simulation of an 11-bit 50 MS/s segmented SAR ADC in 65-nm CMOS technology. The error expressions can be used to select one of the four methods for setting the fine MSBs and to determine β\beta for the required linearity or for implementing digital circuitry for precise error correction.

中文翻译：

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基于无源电荷共享的分段 SAR ADC 分析


本文介绍了基于无源电荷共享的分段逐次逼近寄存器 (SAR) 模数转换器 (ADC) 的理论分析，其中取代了电容式数模转换器 (CDAC) 中的精确参考源由一个比其位电容器大 β\beta 倍的电容器来预充电到参考电平，称为参考电荷储存器（RCR）。分段 SAR-ADC 使用粗略 SAR-ADC 来计算一些最高有效位 (MSB)。引入了四种方法，即使用按位 RCR 的对齐切换（AS）、使用子样本 RCR 的 AS、使用按位 RCR 的检测和跳过对齐切换（DAS-AS）以及使用子样本 RCR 的 DAS-AS设置精细的 MSB。通过对采用 65 nm CMOS 技术的 11 位 50 MS/s 分段 SAR ADC 进行行为建模和电路仿真，得出并验证了有限参考电容导致的参考误差的封闭式解析表达式。误差表达式可用于选择四种方法中的一种来设置精细 MSB 并确定所需线性度的 β\beta 或用于实现精确误差校正的数字电路。