Parallel distributed arithmetic (PDA)-based structures are widely used for high-speed computation of inner product in digital signal processing (DSP) applications. In this article, we have proposed novel PDA-based structures based on an efficient truncation model. To achieve higher bit saving with relatively less truncation error, we present here a novel approach using approximate look-up tables (LUTs), adder trees (ATs), and Wallace-like shift-AT (SAT) with truncated operands to obtain hardware-efficient fixed-width PDA-based inner-product structures. We have three variants of proposed structures based on the proposed truncation approach. We find that the proposed inner-product structure-1 using approximate LUT (ALUT) and approximate AT offers nearly 20% higher bit saving, 20% saving in area-delay product (ADP) and offers relatively less truncation error than the existing structures. The proposed structure-2 using ALUT, ATs, and proposed SAT offers nearly 50% higher bit-saving, 61% ADP saving and offers nearly the same accuracy compared to the existing approximate DA-based structures. Proposed structure-3 offers nearly 60% higher bit saving and calculates outputs with almost the same or marginally less accuracy than the existing structures for higher coefficient word lengths.

中文翻译：

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用于近似内积计算的高效并行基于 DA 的固定宽度设计

基于并行分布式算术 (PDA) 的结构广泛用于数字信号处理 (DSP) 应用中内积的高速计算。在本文中，我们提出了基于有效截断模型的新型基于 PDA 的结构。为了以相对较少的截断错误实现更高的位节省，我们在此提出了一种使用近似查找表 (LUT)、加法器树 (AT) 和具有截断操作数的类似 Wallace 的移位 AT (SAT) 的新方法来获得硬件-高效的固定宽度基于 PDA 的内积结构。我们有基于提议的截断方法的提议结构的三种变体。我们发现建议的内积结构 1 使用近似 LUT (ALUT) 和近似 AT 提供了近 20% 的比特节省，面积延迟乘积 (ADP) 节省 20%，与现有结构相比，截断误差相对较小。与现有的近似基于 DA 的结构相比，使用 ALUT、AT 和建议的 SAT 的建议结构 2 提供了近 50% 的位节省和 61% 的 ADP 节省，并提供几乎相同的精度。提议的结构 3 提供了近 60% 的位节省，并且计算输出的准确度几乎与现有结构相同或略低于更高系数字长的结构。