The von Neumann architecture is approaching its limits in terms of scalability and power consumption. In-memory computation is a possible approach to mitigate this limitation. This brief proposes a configurable 8T static random access memory (SRAM) cell with double word lines and three read ports for in-memory computing. In addition to the normal SRAM function, XOR/XNOR and compound Boolean logic operations of three or four operands, such as AND-OR, AND-OR-INVERT, OR-AND, and OR-AND-INVERT, can be performed in one cycle by fully utilizing the three read ports to obtain 13.2-fJ/bit consumption at 0.6 V. The logic operation frequency is 793 MHz at 1.2 V. The proposed SRAM effectively resolves the bottleneck of the existing in-memory computation schemes that only support compound Boolean logic operations with more than two cycles. In addition, the proposed SRAM array scheme can be configured and used as a binary content-addressable memory or a ternary content-addressable memory for searching operations; it achieves 0.24 fJ/search/bit at 0.6 V in the worst case. At 1.2 V, the searching frequency is up to 813 MHz when searching 128 bits with 65-nm technology.

中文翻译：

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具有双字线和四个操作数的三个读取端口的内存计算

冯诺依曼架构正在接近其可扩展性和功耗方面的极限。内存计算是缓解这种限制的一种可能方法。本简介提出了一种可配置的 8T 静态随机存取存储器 (SRAM) 单元，具有双字线和用于内存计算的三个读取端口。除了普通的SRAM功能外，还可以一次进行AND-OR、AND-OR-INVERT、OR-AND、OR-AND-INVERT等三个或四个操作数的XOR/XNOR和复合布尔逻辑运算。通过充分利用三个读端口在 0.6 V 下获得 13.2-fJ/bit 消耗。 逻辑操作频率在 1.2 V 时为 793 MHz。 所提出的 SRAM 有效解决了现有仅支持复合的内存计算方案的瓶颈具有两个以上周期的布尔逻辑运算。此外，提出的 SRAM 阵列方案可以配置并用作二进制内容可寻址存储器或三进制内容可寻址存储器，用于搜索操作；在最坏的情况下，它在 0.6 V 时达到 0.24 fJ/search/bit。在 1.2 V 时，使用 65-nm 技术搜索 128 位时，搜索频率高达 813 MHz。