In this brief, we investigate device variability in advanced fin field effect transistor (FinFET) static random access memory (SRAM) devices (12 and 7 nm) as a function of drain-to-source (Vds) bias. Drain-induced barrier lowering (DIBL) and the variation in DIBL are found to exhibit a logarithmic dependence with drain bias in the advanced node FinFET devices. Correctly capturing the DIBL and device variation as a function of drain bias is required, as the SRAM operation voltage range is expanded. We show the improved hardware correlation in Vmin yield and the improved slow corner read performance when the Vds-dependent variation is considered.

中文翻译：

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FinFET SRAM 中的偏置相关变化

在本简报中，我们研究了高级鳍式场效应晶体管 (FinFET) 静态随机存取存储器 (SRAM) 器件（12 和 7 纳米）中的器件可变性作为漏源 (Vds) 偏压的函数。发现漏极引起的势垒降低 (DIBL) 和 DIBL 的变化与先进节点 FinFET 器件中的漏极偏压呈对数相关性。随着 SRAM 工作电压范围的扩大，需要正确捕获 DIBL 和器件变化作为漏极偏置的函数。当考虑 Vds 相关变化时，我们展示了改进的 Vmin 产量的硬件相关性和改进的慢角读取性能。