Abstract This work presents a computation efficient image watermarking very large-scale integration (VLSI) architecture with improved robustness and throughput. The computational complexity is reduced by the incorporation of integer DCT, whereas the throughput is improved by the implementation of a four-stage pipeline architecture. Further, in the present work, the secret watermark bits are inserted in the DCT low-frequency coefficients using a mean adaptive threshold value, which not only results in a minimum degradation to the host image quality but also increases the robustness of the proposed algorithm. The VLSI implementation of the proposed algorithm using CadenceⓇ circuit design tools in 180 nm technology demonstrates an overall power consumption of 4.47 mW and a throughput of 2.5 Gbps that are better than the results reported in the literature.

中文翻译：

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具有改进性能的计算高效图像水印架构

摘要 这项工作提出了一种计算效率高的图像水印超大规模集成（VLSI）架构，具有改进的鲁棒性和吞吐量。通过引入整数 DCT 降低了计算复杂度，而通过实施四级流水线架构提高了吞吐量。此外，在目前的工作中，使用平均自适应阈值将秘密水印位插入到 DCT 低频系数中，这不仅导致对主机图像质量的最小化，而且增加了所提出算法的鲁棒性。在 180 nm 技术中使用 CadenceⓇ 电路设计工具对所提出算法的 VLSI 实现表明，总功耗为 4.47 mW，吞吐量为 2。